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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.4k 967

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 448 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 102 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 191 113

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 76

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 352 147

Repositories

Showing 10 of 111 repositories
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,352 MulanPSL-2.0 967 148 193 Updated Oct 27, 2026
  • XSAI Public Forked from OpenXiangShan/XiangShan

    A fork of Xiangshan for AI

    OpenXiangShan/XSAI's past year of commit activity
    Scala 64 MulanPSL-2.0 993 1 2 Updated Oct 27, 2026
  • XSAICache Public Forked from OpenXiangShan/XSCache

    A fork of XSCache for XSAI. Supports High-Bandwidth L2 Cache design.

    OpenXiangShan/XSAICache's past year of commit activity
    Scala 2 8 0 1 Updated Oct 27, 2026
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 166 BSD-3-Clause 96 18 103 Updated Oct 27, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 352 147 40 45 Updated Oct 27, 2026
  • XSCache Public

    Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.

    OpenXiangShan/XSCache's past year of commit activity
    Scala 3 8 0 11 Updated Oct 27, 2026
  • AME_spike Public
    OpenXiangShan/AME_spike's past year of commit activity
    C 44 9 0 0 Updated Oct 27, 2026
  • gsim Public
    OpenXiangShan/gsim's past year of commit activity
    C++ 91 14 2 8 Updated Oct 27, 2026
  • TraceRTL Public

    Trace-driven CPU RTL performance evaluation for robust simulation, broad application coverage, and rapid prototyping.

    OpenXiangShan/TraceRTL's past year of commit activity
    C++ 0 0 0 0 Updated Oct 27, 2026
  • Talks-and-Publications Public

    Talks and Publications archive for the XiangShan Team

    OpenXiangShan/Talks-and-Publications's past year of commit activity
    TeX 3 CC-BY-4.0 1 0 0 Updated Oct 27, 2026