Fix RISC-V vector state preservation across context switches by whensun · Pull Request #145 · IBM/ACE-RISCV

whensun · 2026-10-30T03:12:41Z

Description of the changes

This PR fixes missing RISC-V Vector architectural state preservation during context switches between confidential VMs and the hypervisor.

Previously, vector registers and control/status registers were not saved and restored during context switches, potentially causing vector state corruption.

This PR introduces vector state preservation for:

Vector registers v0–v31
Vector CSRs vl, vtype, vstart, and vcsr
Vector fixed-point state vxrm and vxsat through vcsr

The implementation integrates vector state management into the existing hart architectural state and context-switching mechanisms.

Type of change

Bug fix (non-breaking change which fixes an issue)
New feature
Breaking change
Refactorization

How to test this PR?

Build ACE-RISCV with the RISC-V Vector extension enabled.
Initialize vector registers and CSRs with known values.
Trigger context switches between confidential VMs (VS → VS).
Trigger context switches between a confidential VM and the hypervisor (VS → HS → VS).
Verify that the original vector state is restored.

Signed-off-by: whensun <theodoruswensanfebruanto025@gmail.com>

wojciechozga · 2026-11-06T09:34:38Z

    csrs: ControlStatusRegisters,
    fprs: FloatingPointUnit,
    sstc: SupervisorTimerExtension,
+    vector: VectorUnit,


to follow naming convention, should we name it vrs (vector registers) instead of vector?

Done. Renamed vector to vrs in HartArchitecturalState and updated all related accessors and references.

wojciechozga · 2026-11-06T09:49:09Z

        }
+
+        if HardwareSetup::is_extension_supported(HardwareExtension::VectorExtension) {
+            self.csrs().mstatus.read_and_set_bits(SR_VS_DIRTY);


please add a comment (like in FPU-related code) explaining that SR_VS_DIRTY flag enables the vector unit in mstatus, allowing accessing vector-related registers and instructions.

Done. Added comments explaining that setting SR_VS_DIRTY enables access to vector registers and instructions.

wojciechozga · 2026-11-06T11:54:15Z

+                    asm!(
+                        ".option push",
+                        ".option arch, +v",
+                        concat!("vs1r.v v", stringify!($index), ", ({address})"),


vs8r.v stores more registers at a time what reduces the total number of instructions per context switch. An analog approach should be followed for the load from memory

Done. Replaced the 32 individual register store/load instructions with four vs8r.v instructions and four vl8re8.v instructions.

wojciechozga · 2026-11-06T11:56:03Z

+
+        assert!(vlenb > 0);
+
+        let length = NUMBER_OF_VECTOR_REGISTERS.checked_mul(vlenb).expect("Invalid vector register size");


Please return an error instead of panicking

I've changed VectorUnit::empty() to return Result<Self, Error>, with explicit error handling for invalid vector register sizes and allocation failures. I've updated the callers to propagate these errors.

wojciechozga · 2026-11-06T12:01:28Z

+    vlenb: usize,
+    vl: usize,
+    vtype: usize,
+    vstart: usize,
+    vcsr: usize,


please reuse ReadWriteRiscvCsr similarly to FPU code. Then minimize custom assembly blocks by calling respective functions.

wojciechozga · 2026-11-06T12:04:27Z

+    }
+
+    pub unsafe fn save_in_main_memory(&mut self) {
+        unsafe { self.validate_vlenb() };


Do we need this checks for every context switch? Wouldn't it be enough to check vlenb once? If vlenb could differ among harts, we should then check it when deciding if V ext should be supported in the initialization procedure. Otherwise, the validate_vlenb should return an error and not panic on a mismatch.

I've moved the VLEN validation to initialization instead of checking it during every context switch. The boot hart records the expected vlenb, and each hart validates its value during setup. Invalid or inconsistent values return an error from the validation function.

wojciechozga

Thanks for this PR. I left a few comments, please have a look

whensun · 2026-11-07T21:50:32Z

Hi Wojciech,

Thank you for the review. I have addressed all six comments in the latest commit.

The changes include:

Renamed vector to vrs.
Added comments explaining SR_VS_DIRTY.
Replaced individual vector register loads/stores with vs8r.v and vl8re8.v.
Added error handling for vector state initialization.
Reused ReadWriteRiscvCsr for vector CSRs.
Moved VLEN validation to initialization, including per-hart compatibility checks.

Validation:

Rust compilation: PASS
OpenSBI firmware build: PASS
ACE-RISCV regression 8 test cases: PASS

The regression test cases cover vector CSR preservation across VS-to-VS and VS-to-HS-to-VS context switches.

Could you please review the updated implementation when you have a chance?

Thanks!

Signed-off-by: whensun <theodoruswensanfebruanto025@gmail.com>

whensun added 2 commits October 29, 2026 20:04

Fix RISC-V vector state preservation across context switches

60be645

Signed-off-by: whensun <theodoruswensanfebruanto025@gmail.com>

Remove temporary VectorUnit diagnostics

f8137af

Signed-off-by: whensun <theodoruswensanfebruanto025@gmail.com>

whensun mentioned this pull request Nov 4, 2026

Increase ACE OpenSBI hart stack size to 16 KiB #146

Merged

1 of 4 tasks

Fix false-positive RISC-V Vector extension detection

dbc8b67

Signed-off-by: whensun <theodoruswensanfebruanto025@gmail.com>

wojciechozga reviewed Nov 6, 2026

View reviewed changes

wojciechozga requested changes Nov 6, 2026

View reviewed changes

wojciechozga assigned wojciechozga and unassigned wojciechozga Nov 6, 2026

Address review feedback on vector state preservation

d237db4

Signed-off-by: whensun <theodoruswensanfebruanto025@gmail.com>

whensun force-pushed the fix/vector-context-switch branch from 9854224 to d237db4 Compare November 7, 2026 21:52


		assert!(vlenb > 0);

		let length = NUMBER_OF_VECTOR_REGISTERS.checked_mul(vlenb).expect("Invalid vector register size");

Conversation

whensun commented Oct 30, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Description of the changes

Type of change

How to test this PR?

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

wojciechozga Nov 6, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

wojciechozga Nov 6, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

wojciechozga left a comment

Choose a reason for hiding this comment

Uh oh!

whensun commented Nov 7, 2026

Uh oh!

Reviewers

Uh oh!

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

whensun commented Oct 30, 2026 •

edited

Loading

wojciechozga Nov 6, 2026 •

edited

Loading

wojciechozga Nov 6, 2026 •

edited

Loading