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CFDFC duplication for select units - #1144
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This at the moment solves #1018, since we now have constraints for every single edge there is no deadlock anymore |
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New approach:
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Jiahui17
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Also, if you add "fixes #1018", github will automatically link this pull request to the issue when this PR gets merged, GH will close the issue as completed |
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…uts for select units, we now create only one additional CFDFC for each CFDFC that contains a select unit
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In FPGA20, section 4.4, when discussing select units it was mentioned that
The current implementation, simply assumes that the true input is the least executed one and ignores the false one.
dynamatic/lib/Transforms/BufferPlacement/Utils/BufferPlacementMILP.cpp
Line 798 in e47e9c2
In this version, we create an additional CFDFC for each one that contains a select unit. We set the numbe rof executions of the "original" CFDFC to 0, such that it has no impact on the objective
dynamatic/lib/Transforms/BufferPlacement/Utils/BufferPlacementMILP.cpp
Line 1447 in e47e9c2
This way we still get timing constraint sfor each channel, but avoid influencing the buffer placement. In the other CFDFC, we "remove" one of the two channels. Currently, we still delete the false input, assuming it is always the least executed one.
Next, it would probably be a good idea to get actual data on which branch is executed more, such that we can prioritize the most executed branch. Alternatively, we could follow the approach outlined in FPGA20
Fixes #1018